SiP Packaging Adhesive Guide

Introduction to SiP Adhesive Selection

System in Package (SiP) integrates multiple semiconductor die, passive components, and sometimes MEMS sensors into a single package. This heterogeneous integration approach is growing rapidly in mobile, IoT, wearable, and automotive electronics.

Unlike single-chip packages, SiP assembly involves multiple adhesive bonding steps — each with different material requirements. Selecting the right adhesive for each step is critical for yield, reliability, and production throughput.

Adhesive Functions in SiP

1. Die Attach

Die attach adhesive bonds semiconductor die to the substrate or to another die (in stacked configurations). Key requirements:

• Controlled bond line thickness — Typically 10-50μm for die stacking
• Low voiding — Voids cause hot spots and reduce thermal conductivity
• Low stress — Prevents thin die cracking (especially for die <100μm thick)
• Controlled fillet — Prevents adhesive bleeding onto bond pads

2. Underfill

When SiP includes flip chip interconnects, capillary underfill protects the solder joints — same function as in standalone flip chip packages, but with additional constraints from the multi-component assembly flow.

3. Board Reinforcement

Structural adhesive applied to substrate edges or under large passive components to prevent board-level flexural failure and improve drop-test reliability.

4. Module Bonding

For camera modules, sensor modules, and optical SiP, adhesives must provide precise alignment, optical clarity (for light-path applications), and environmental sealing.

SiP Adhesive Selection Matrix

Material Selection Criteria

Cure Temperature

SiP often includes temperature-sensitive components. Adhesive cure temperature must be below the damage threshold of all assembled components. COFA offers cure temperatures from 80°C (COFA 3100H) to 150°C, providing flexibility for different assembly sequences.

Multi-Step Process Compatibility

SiP assembly involves multiple thermal steps (die attach cure → wire bond → reflow → underfill cure). Each adhesive must survive subsequent thermal steps without degradation. COFA adhesives are designed with staged cure profiles — B-stage snap cure for die attach, followed by full cure that tolerates subsequent reflow temperatures.

Stress Management

Multi-die SiP packages accumulate thermal stress from each bonded interface. Low-modulus, low-CTE adhesives minimize stress buildup. This is especially critical for thin die (<75μm) that are prone to cracking.

Dispensing Precision

SiP assembly requires precise adhesive placement to avoid contamination of wire bond pads, flip chip bumps, or optical surfaces. COFA formulations provide stable thixotropic behavior for precise dot and line dispensing.

Process Flow Example: Mobile SiP

1. Step 1: Die attach — Logic die bonded to substrate using COFA 5001S, snap cure at 150°C/30s
2. Step 2: Wire bond — Gold or copper wire bonding to substrate pads
3. Step 3: Die attach (stacked) — Memory die bonded on top of logic die
4. Step 4: Wire bond (top die)
5. Step 5: Board reinforcement — COFA 3100H applied to substrate edges, cure at 80°C/30min
6. Step 6: Mold encapsulation — Transfer mold or compression mold
7. Step 7: Singulation — Dicing into individual SiP packages