Flip Chip Underfill Explained

Introduction

Flip chip underfill is one of the most critical — yet often underappreciated — materials in semiconductor packaging. It is the adhesive that fills the gap between a flip chip die and its substrate, transforming a mechanically vulnerable array of solder bumps into a robust, reliable interconnect system.

This article explains what flip chip underfill is, why it's needed, how it works, and what material properties packaging engineers should consider when selecting an underfill formulation.

Why Is Underfill Needed?

In flip chip packaging, the die is mounted face-down on the substrate, connected through an array of solder bumps (or copper pillars). Without underfill, these tiny interconnects bear all the thermomechanical stress caused by the CTE mismatch between silicon (~2.6 ppm/°C) and organic substrate (~15-18 ppm/°C).

During thermal cycling — which every electronic device experiences in normal operation — this CTE mismatch creates shear stress on the solder joints. The joints at the die corners, farthest from the neutral point (DNP), experience the highest stress and are the first to fail.

Underfill solves this by distributing stress across the entire die-substrate interface rather than concentrating it on individual bumps. This can improve solder joint fatigue life by 10-100x, depending on the package geometry and thermal conditions.

How Capillary Underfill Works

The most common type of flip chip underfill is capillary underfill (CUF). The process works as follows:

1. Solder reflow — The flip chip die is placed and reflowed to create solder interconnects.
2. Flux cleaning — Residual flux is cleaned (for clean processes) or left in place (no-clean flux).
3. Dispensing — Liquid underfill is dispensed along one or two edges of the die using a needle dispenser.
4. Capillary flow — Surface tension and capillary action draw the underfill through the bump array, filling the gap between die and substrate.
5. Cure — The filled assembly is placed in an oven for thermal cure (typically 120-150°C for 30-60 minutes).

The result is a fully encapsulated bump array with a continuous epoxy matrix surrounding every interconnect.

Key Material Properties

Viscosity

Controls flow rate and void formation. Lower viscosity enables faster fill and longer flow distances (important for large die), but too low can cause excessive bleed-out. Typical range: 3-30 Pa·s at dispensing temperature.

CTE (Coefficient of Thermal Expansion)

The CTE of cured underfill should be between that of solder and substrate to gradually transition the thermal strain. Typical target: 25-40 ppm/°C below Tg (α1), achieved by controlling filler content.

Tg (Glass Transition Temperature)

Above Tg, the modulus drops and CTE increases sharply. For reliability, Tg should be above the maximum operating temperature. Target: >130°C for consumer, >150°C for automotive.

Filler Content and Size

Silica fillers reduce CTE and improve modulus. Filler size must be smaller than the bump pitch gap — typically sub-5μm for fine-pitch (<100μm) applications. Filler content ranges from 50-70% by weight.

Adhesion

Strong adhesion to die passivation, solder mask, and bump metallurgy is essential. Delamination at any interface creates a stress concentration that propagates cracks during thermal cycling.

When to Use Flip Chip Underfill

• FCBGA packages with large die (>10mm × 10mm)
• HBM packaging with ultra-fine-pitch micro-bumps
• 2.5D interposer packages with multiple chiplets
• FC-CSP packages requiring drop-test reliability
• Any flip chip package subjected to thermal cycling reliability requirements